1. Field of the Invention
The present invention relates to an analog to digital converter.
2. Prior Art
The inventors of the present invention proposed a voltage-driven analog to digital (A/D) converter of low electrical power consumption used in a handy terminal for a digital mobile communication, in Japanese Patent Publication Hei09-083364. This A/D converter includes a plurality of comparators consisting of a complementary metal-oxide-semiconductor (CMOS) inverter and a plurality of threshold setting circuits consisting of capacitive couplings connected to inputs of the comparators. Analog input voltages are input to the threshold setting circuits, and outputs of the comparators are weighted by predetermined weights and are input to threshold setting circuits of lower bits. A high accuracy and low power consumption are realized.
However, the conventional A/D converter defines the thresholds of the comparators by logical thresholds of the CMOS inverters, therefore, the outputs of the A/D converter is unstable when the input voltage is nearly equal to the threshold. And the threshold has a deviation due to manufacturing conditions.
Besides the above A/D converter, a sequential A/D converter is well-known, which includes a comparator for comparing an input voltage with a threshold voltage. Then one bit of a digital data is generated and the bit is converted into an analog data to be fed back to the comparator. This process is repeated for generating the total bits of a digital data, therefore, it takes a log time.
The present invention has an object to provide a stable A/D converter of high speed, being free from deviation depending on manufacturing condition.
An A/D converter according to the present invention